This invention relates to a field effect transistor (FET). More particularly, although not exclusively, it relates to FETs such as MISFETs made from narrow bandgap semiconductor materials, ie bandgap EG in the region of or less than 0.5 eV. It is also relevant to FETs made from wider bandgap materials for use at elevated operating temperatures above ambient temperature.
Narrow bandgap semiconductors such as indium antimonide (InSb) have useful properties such as very low electron effective mass, very high electron mobility and high saturation velocity. These are potentially of great interest for ultra high speed applications. InSb in particular is a promising material for fast, very low power dissipation transistors, because its electron mobility xcexce at low electric fields is nine times higher than that of GaAs and its saturation velocity vsat is more than five times higher, despite GaAs having good properties in these respects. InSb is also predicted to have a large ballistic mean free path of over 0.5 xcexcm. This suggests that InSb has potential for high speed operation at very low voltages, allowing low power consumption, which would make it ideal for portable and high-density applications. Some of the properties of Silicon, GaAs and InSb at 295 K (ambient temperature) are compared in Table 1 as follows:
Until recently, the potentially valuable properties of InSb have been inaccessible at ambient temperatures due to its low band-gap and consequently high intrinsic carrier concentration (xcx9c2xc3x971016 cmxe2x88x923), which is six and nine orders of magnitude above those of Si and GaAs respectively. This leads to InSb devices exhibiting high leakage currents at normal operating temperatures at or near ambient temperature of 295K, where the minority carrier concentration is much greater than the required value at normal doping levels. It was thought for many years that this was a fundamental problem which debarred InSb and other narrow bandgap materials from use in devices at ambient temperature and above. The problem was however overcome by means of the invention the subject of U.S. Pat. No. 5,382,814, which discloses a non-equilibrium metal-insulator-semiconductor field effect transistor (MISFET) using the phenomena of carrier exclusion and extraction to reduce the intrinsic contribution to the carrier concentration well below the equilibrium level. This prior art MISFET is a reverse-biased p+p+xcfx80n+ structure, where p denotes an InSb layer, p is a strained In1xe2x88x92xAlxSb layer (underlined p indicates wider band-gap than p), xcfx80 indicates a weakly doped p-type region that is intrinsic at ambient operating temperature, and the + superscript indicates a heavy dopant concentration; these four layers define three junctions between respective adjacent layer pairs, ie p+p+, p+xcfx80 and xcfx80n+ junctions respectively. The active region of the device is the xcfx80 region, and minority carriers are removed from it at the xcfx80n+ junction acting as an extracting contact. The p+xcfx80 junction is an excluding contact inhibiting re-introduction of these carriers. In consequence, under bias applied to the device the minority carrier concentration falls, and the majority carrier concentration falls with it to preserve charge neutrality. This produces carrier concentrations below intrinsic levels. A similar effect is produced by cooling. Here the expression xe2x80x9cintrinsicxe2x80x9d is used with its normal construction to mean that carriers arise largely from activation of valence states, and approximately equal numbers of minority and majority carriers are present in the semiconductor material. This expression is sometimes wrongly used for extrinsic material (eg Si) to indicate simply that the doping level is low, whereas in extrinsic material carriers arise largely from activation of either donor or acceptor states and one type of carrier (electrons or holes) predominates.
The device disclosed in U.S. Pat. No. 5,382,814 was a 1 xcexcm recessed-gate enhancement-mode MISFET structure. For investigation purposes a variety of devices of this kind were produced. It was predicted theoretically that the frequency fT at which the current gain would fall to unity in a device of this kind would be 55 GHz, but measured values were obtained which were only in the region of 10 GHz. The value of fT is treated as a figure of merit by those skilled in the art of high frequency transistors. The best value of fT obtained for any of these devices was 17 GHz, despite attempts to limit device capacitance associated with overlap of gate contact metal on to source and drain regions. This indicates that it is difficult to realise the full high frequency potential of InSb MISFETs.
It is an object of the invention to provide an alternative form of FET capable of exhibiting an improved value of current gain cut-off frequency fT.
The present invention provides a field effect transistor (FET) of the kind including a region having intrinsic conductivity when unbiased at an operating temperature of the FET and biasing means for depressing the intrinsic contribution to the charge carrier concentration in the intrinsic region, characterised in that the FET also includes means for defining a channel extending between a source region and a drain region with any intervening departure from channel straightness being not more than 50 nm in extent, as appropriate to enable a high value of current gain cut-off frequency to be obtained. Any such departure from channel straightness is preferably not more than 5 nm in extent; the expression xe2x80x9cextentxe2x80x9d means the maximum height differential between any two regions of the channel, eg its central region and a region adjacent to the source or drain.
The invention provides the advantage that it is capable of providing greatly enhanced values of current gain cut-off frequency compared to the prior art, indicating greatly improved high frequency performance. MISFETs in particular in accordance with the prior art were found to have disappointing performance at high frequency much below theoretical expectations. The reason for this was originally not understood. However, a number of hypotheses were investigated in an attempt to resolve the problem. One of these hypotheses was that over-etching a MISFET gate recess might degrade high frequency performance. Devices of the invention produced without an intervening gate groove intrusion have exhibited much better performance at high frequency, and it is inferred that the hypothesis of the deleterious effect of gate grooving on performance is confirmed.
In one aspect, the FET of the invention is an enhancement mode MISFET; it may incorporate source and drain regions which are produced by introduction of heavy doping into a layer incorporating the intrinsic region The source and drain regions may be produced by implantation, diffusion doping, alloying or introduction of damage. The intrinsic region may be residually p-type doped and form extracting contact means with the source and drain regions, the channel formed in the intrinsic region in response to bias being n-type.
In a preferred embodiment, the intrinsic region has an interface with a barrier region itself having an interface with a base region, and the intrinsic, barrier and base regions (106, 104, 102) being of like conductivity type and the barrier region being of relatively wider bandgap than the intrinsic and base regions and providing an excluding contact to the intrinsic region.
The FET of the invention may include a gate contact insulated from and extending at least over that part of the intrinsic region between the source and drain regions to define an enhancement channel therebetween in operation. The base region may be of p+ InSb with a dopant concentration of at least 5xc3x971017 cmxe2x88x923; the barrier region may be of p+ In1xe2x88x92xAlxSb with x in the range 0.05 to 0.25 with a dopant concentration of at least 5xc3x971017 cmxe2x88x923; the intrinsic region may be of xcfx80 InSb with a dopant concentration of less than 5xc3x971017 cmxe2x88x923, preferably 1xc3x971015 cmxe2x88x923 to 5xc3x971016 cmxe2x88x923 and the source and drain regions may be of n+ InSb with a dopant concentration of at least 5xc3x971017 cmxe2x88x923.
The base, barrier and intrinsic regions are preferably successively disposed in a layer structure, the source and drain regions being produced by implantation, diffusion alloying or damage in the intrinsic region, and the intrinsic region preferably has a substantially flat surface portion supporting a gate insulation layer and a gate contact.
In another aspect, the FET of the invention is a depletion mode MISFET having an associated channel region. It may incorporate source and drain regions which are heavily doped outgrowths formed upon either the intrinsic region or the channel region; these regions may alternatively be produced by implantation, diffusion, alloying or introduction of damage. They may define therebetween a gate recess accommodating a gate contact.
The intrinsic region may be p-type and either itself or the channel region may form extracting contact means with the source and drain regions.
In a preferred embodiment, the intrinsic region has an interface with a barrier region which itself has an interface with a base region, the intrinsic, barrier and base regions being of like conductivity type and the barrier region being of relatively wider bandgap than the intrinsic and base regions and providing an excluding contact to the intrinsic region. In this embodiment:
the base region may be of p+ InSb with at least 5xc3x971017 acceptors cmxe2x88x923;
the barrier region may be of p+In1xe2x88x92xAlxSb with x in the range 0.05 to 0.25 and at least 5xc3x971017 acceptors cmxe2x88x923;
the intrinsic region is of xcfx80 InSb with less than 5xc3x971017 acceptors cmxe2x88x923, preferably in the range 1xc3x971015 cmxe2x88x923 to 5xc3x971016 cmxe2x88x923; and
the source and drain regions are of n+ InSb with at least 5xc3x971017 donor cm3.
The intrinsic region may support a channel region, the base, barrier, intrinsic and channel regions being successively disposed in a layer structure, the source and drain regions being grown upon the channel region and the channel region having a substantially flat surface portion supporting a gate insulation layer and a gate contact. The source and drain regions may define therebetween a gate recess, the channel region having a surface portion at an end of the recess supporting the gate insulation layer and gate contact.
The channel region may lie between parts of the intrinsic region, the latter forming extracting contact means in combination with the source and drain regions.
The base, barrier and intrinsic regions are preferably successively disposed in a layer structure, the intrinsic region containing the channel region and supporting the source and drain regions.
The biasing means for depressing the intrinsic contribution to the carrier concentration in the intrinsic region is preferably arranged to bias the FET at a point of infinite differential impedance where the variation of gate threshold voltage due to substrate bias voltage variations is minimised.
In an alternative aspect, the invention provides a method of making an FET of the kind comprising biasing means for depressing the intrinsic contribution to the charge carrier concentration in an intrinsic region thereof, characterised in that the method includes defining a channel extending between a source region and a drain region such that any intervening departure from channel straightness is not more than 50 nm in extent, as appropriate to enable a high value of current gain cut-off frequency to be obtained. Any such departure from channel straightness is preferably not more than 5 nm in extent.